A new concept for spatially divided Deep Reactive Ion Etching with ALD-based passivation

Conventional Deep Reactive Ion Etching (DRIE) is a plasma etch process with alternating half-cycles of 1) Si-etching with SF6 to form gaseous SiFx etch products, and 2) passivation with C4F8 that polymerizes as a protecting fluorocarbon deposit on the sidewalls and bottom of the etched features. In this work we report on a novel alternative and disruptive technology concept of Spatiallydivided Deep Reactive Ion Etching, S-DRIE, where the process is converted from the time-divided into the spatially divided regime. The spatial division can be accomplished by inert gas bearing ‘curtains’ of heights down to ~20 m. These curtains confine the reactive gases to individual (often linear) injection slots constructed in a gas injector head. By horizontally moving the substrate back and forth under the head one can realize the alternate exposures to the overall cycle. A second improvement in the spatially divided approach is the replacement of the CVD-based C4F8 passivation steps by ALD-based oxide (e.g. SiO2) deposition cycles. The method can have industrial potential in cost-effective creation of advanced 3D interconnects (TSVs), MEMS manufacturing and advanced patterning, e.g., in nanoscale transistor line edge roughness using Atomic Layer Etching. Introduction 3D through-silicon vias (TSVs) date back to two patents in the 1960s [1, 2], cf. Fig. 1. Yet, it is only now with the continuous on-chip scaling reaching the point where Moore’s Law (essentially an economic law) approaches its limits that TSV technology receives increasing interest for 3D integration [3]. Other drivers next to cost reduction are the reduced form factor and the increased performance of TSV-connected stackeddie devices, such as reduced RC delay and low power consumption. TSV technology is also accelerating the rapidly growing market of microelectromechanical systems (MEMS) by enabling the interconnection of multifunctional chips stacked in a heterogeneously 3D-integrated System-in-Package (i.e. the so-called ‘More than Moore’ domain). Today, the industrial technology of choice for etching both TSV and MEMS structures in silicon is Deep Reactive Ion Etching (DRIE). Figure 1. TSV structures proposed in Shockley’s patent [1]. E-MRS 2012 Spring Meeting: Symposium M IOP Publishing IOP Conf. Series: Materials Science and Engineering 41 (2012) 012001 doi:10.1088/1757-899X/41/1/012001 Published under licence by IOP Publishing Ltd 1 Spatially divided Deep Reactive Ion Etching: a new concept The conventional technology of choice for silicon DRIE etching is the room temperature Bosch process [4, 5] illustrated in Fig. 2a. This process consists of two alternating half-cycles: 1) etching with SF6 plasma, and 2) passivation of the sidewalls and bottom of the etched features with a protecting -(C2F4)nfluorocarbon, PTFElike) polymer liner deposited from C4F8 plasma. Figure 2. a) Conventional Bosch etch process scheme with temporal switching of consecutive etch and passivation half-cycles. The horizontal bar in grey represents a pre-patterned hard mask; (b) alternative spatial process modes with C4F8 passivation; (c) alternative with spatial ALD SiO2 passivation of a wafer which moves horizontally back and forth under spatially divided reaction zones. Blue arrows pointing upwards indicate exhaust lines. Notice the difference in height of the gas bearing compartments (down to ~20 m) and the plasma compartments (order ~mm); not to scale. The first half-cycle is an ion-assisted isotropic etch step with SF6 plasma. It would proceed if noninterrupted mainly by the non-directional F-containing radicals to form volatile SiFx products that are pumped off. In order to minimize the lateral etching component the etch steps are quickly interrupted by C4F8 passivation steps. During each etch step a bias voltage is applied to the substrate holder. This causes a directional physical ion bombardment from the plasma onto the substrate which sputters the polymer off the feature’s bottom part, thus leaving the sidewall passivation intact, and enabling the anisotropic etching. The etch and passivation cycle times are each typically 1-10 s with 0.1-1 m etched per cycle. The process enables plasma etching of deep vertical microstructures (aspect ratios AR 20:1) in silicon with etch rates of typically 3-5 m/min, and selectivities up to ~200:1 against a hard oxide mask (usually SiO2) [6]. An accelerated etch alternative is to convert the above process from its temporal (i.e. time-separated) into the spatially separated regime [7]. The spatial separation can be accomplished by inert gas (e.g. N2) bearing ‘curtains’ of heights down to ~20 m, or even smaller (Fig. 2b). These curtains confine the reactive gases to individual (often linear) injection zones constructed in a gas injector head. By horizontally moving the substrate back and forth under the multiple injector head one can create the alternate exposures needed to complete the overall cycle. The optimum pressure in each injection slot is obtained by balancing the various gas flows which are injected into and exhausted from the slots, and by a proper design of the distance between the various slots and the gas bearing gap height (a smaller gap causes a larger pressure field gradient between the various channels). The passivation step in spatial DRIE: ALD-based, low-pressure or atmospheric The selected mask material generally affects etch rate, undercutting, and surface quality of etched features [8]. Oxidic ALD-deposited hard masks like Al2O3 are reported to have lower pinhole density and thus superior etch selectivity than conventionally deposited etch hard masks [9, 10]. Thus a further improvement in the spatial approach can be expected from the replacement of the CVD-based C4F8 passivation steps by ALDE-MRS 2012 Spring Meeting: Symposium M IOP Publishing IOP Conf. Series: Materials Science and Engineering 41 (2012) 012001 doi:10.1088/1757-899X/41/1/012001